1. Field
The present disclosure relates to a test pattern of a semiconductor device.
2. Description of the Related Art
In order for a semiconductor device to operate normally, alignment, isolation, or electrical connection between constituent elements that constitute the semiconductor device should satisfy their requirements. Further, since design rule reduction and multilayer wiring structures are typically used for high integration of the semiconductor device, the alignment, isolation, or electrical connection between the respective constituent elements as described above become important factors that directly exert an influence on the yield of the semiconductor device. Accordingly, various tests for testing whether the respective constituent elements are formed and operated as they are designed are performed when or before several steps of a process for fabricating a semiconductor device are performed.
As one of scaling techniques to heighten the density of a semiconductor device, a multi-gate transistor has been proposed, in which a fin-shaped or nanowire-shaped silicon body is formed on a substrate and a gate is formed on a surface of the silicon body.
Since such a multi-gate transistor uses a three-dimensional (3D) channel, it is easy to perform scaling. Further, current control capability can be improved even without increasing a gate length of the multi-gate transistor. In addition, a short channel effect (SCE) that an electric potential of a channel region is affected by a drain voltage can be effectively suppressed.